1. Field of the Invention
The present invention relates to semiconductor memories, in particular, to non-volatile semiconductor memories such as Erasable Programmable Read Only Memory (EPROM), or Electrically Erasable and Programmable Read Only Memory (EEPROM).
2. Description of the Related Art
Metal Oxide Semiconductor (MOS) semiconductor memory devices, specifically, floating gate MOS transistor structures used as memory cells, are well known in the art. Each of these devices is operated by charging or discharging a floating gate. The charged floating gate affects the underlying channel which in turn determined the conductivity between the drain to the source. In EPROM technology, the floating gate is charged by hot-electron injection from the channel and discharged by ultra-violet light illumination. In EEPROM technology, the floating gate is both charged or discharged by the Fowler-Nordheim (F-N) tunneling effect. Recently, there is a new generation of devices called the flash EEPROM which utilizes the hot-electron injection from the channel for the charging of the floating gate, and the Fowler-Nordheim tunneling effect for the discharging of the floating gate.
FIG. 1a shows a top plan view of a conventional floating gate MOS cell which is denoted by reference numeral 12. FIG. 1b shows a cross-sectional view taken along line 1b-1b of FIG. 1a. FIG. 1c shows another cross-sectional view taken along line 1c--1c of FIG. 1a. The cell of FIGS. 1a-1c includes a P-type silicon substrate 1 having an N.sup.+ -type diffusion drain 2 and source 3 formed in the substrate. Between drain 2 and source 3 is a channel region 4. A floating gate 6 is dielectrically disposed atop insulating layer 5 and extends over to the field oxide 9. A select gate 8 formed on an insulating layer 7 on the top of floating gate 6 and crosses over field oxide 9. A contact 10 formed atop the drain 2 provides connection to a metal bit line 11.
FIG. 2 is a schematic diagram of an equivalent circuit of the memory cell shown in FIGS. 1a-1c. In an memory cell array with the aforementioned cell construction, the N.sup.+ -type source 3 is connected to a source line SL, while the N.sup.+ -type drain 2 is connected to a bit line BL. Moreover, the select gate 8 is connected to a select gate line SGL. When such a cell is used as a flash EEPROM device, insulating layer 5 is intentionally designed with a thin geometry, for example, 11 nanometers. An illustration of such a design can be found in A. Umezawa et al., IEEE Journal of Solid State Circuits (JSSC), vol. 27, No. 11, November 1991, PP1540-1546; or in T. Jinbo et al., IEEE JSSC, vol. 27, No. 11, November 1992, PP1547-1553. FlG.3 shows a set of exemplary voltage values at various terminals for the programming and deprogramming of the cell, along with the corresponding change in threshold voltages VT of the MOS transistor 12. The main disadvantage of this type of memory cell is that it is space consuming. As a consequence, number of cells integrated per unit area in the semiconductor substrate is relatively low. Moreover, during the deprogramming process, threshold voltage VT of the cell needs to be constantly checked and deprogrammed for an assurance that the threshold voltage VT of transistor 12 falls within a predetermined window. In this particular case, the predetermined window is from +1 Volt to +3 Volts. Phrased differently, threshold voltage VT of transistor 12 can not assume a negative value. The main reason is that if the threshold voltage VT of transistor 12 falls below zero volt, transistor 12 is at "ON" state with a conductive channel 4, resulting in bit line BL and source line SL being electrically shorted together. The consequence is twofold. First, floating gate MOS transistor 12 are normally arranged in a matrix format with bit line BL in each of the matrix columns connected together, and with the select gate line SGL of each of the matrix rows connected together. Source line SL of all the transistors are shorted together to ground potential. A conductive transistor 12 in any of the column will yield a false read operation in the particular column. In addition, a shorted channel 4 in transistor 12 effectively clamps the bit line BL to the ground potential. Thus any transistor 12 in the same column can not be programmed as it needs a +5 Volts on bit line BL as one of the conditions for programming as shown in FIG. 3.
Thus, the requirement imposed on prior art transistor 12 that it must fall with a predetermined threshold voltage window after deprogramming places further complication in design with extra circuitries.
In view of the drawbacks with the aforementioned memory cells, there are EPROM and EEPROM cells designed in the past with better performances. These cells are fabricated with thin field oxide regions and contacts. Examples of such cells are taught in R. Kazerounim et al., IEDM Technical Digest 1991, paper 11.5.1, pp 311-314; in B. J. Woo et al., IEDM Technical Digest 1990, paper 5.1.1, pp 91-94; in Y. Yamauchi et al., IEDM Technical Digest 1991, pp 319-322; or in Gill, U.S. Pat. No. 5,051,796, issued Sep. 24, 1991. These cells offer various improvements over the earlier structures. However, to attain a high gate capacitance coupling ratio, which is defined as the ratio of the coupled floating gate voltage to the active control gate voltage, the area of the main cell needs to be built with a large geometry. consequently, a large device consumes more space in a semiconductor substrate and increases the susceptibleness to noise. The reduction in noise immunity vulnerably exposes the memory cell to spurious signals which occur frequently during the programming process.